1. Field of the Technology
This invention relates to a method of making semiconductor integrated circuit devices, more particularly to a method of making semiconductor integrated circuit devices comprising resistance devices of a high sheet resistance.
2. Prior Art
Conventionally, a diffusion resistor having a sheet resistance of 200-500.OMEGA./.quadrature. has been often used as a resistor in semiconductor integrated circuit devices (hereinafter referred to as IC devices). When a resistor having a resistance more than 10K.OMEGA. is formed by using such a resistor having a low sheet resistance, the resultant resistor necessitates a large area in an IC device, thereby resulting in increase of a stray capacitance. Therefore, it is difficult in the conventional IC device to increase the integration degree and to obtain a high operational speed therein.
An example of the conventional method of making a resistor having a high sheet resistance in an IC device is elucidated by referring to FIG. 1(a)-FIG. 1(e). These figures are cross-sectional views illustrating the belowmentioned steps A to E of the conventional making method:
Step A: As a first step, a semiconductor substrate 1 of e.g. n-type single crystalline silicon is oxidized to form an oxide film layer. By a known photoetching method, windows 3 are opened to form impurity layers 4, thus the oxide layer is divided into oxide layers 2 and 2'. Impurity atoms, e.g. boron of a high concentration are diffused through the windows 3 to form the impurity layers 4 to be in contact with a resistor region at a large depth. The above impurity diffusion is carried out by a heat treatment at a high temperature between 1,050.degree.-1,150.degree. C.--FIG. 1(a).
Step B: The oxide layer 2' is removed and a window 5 is formed by a known photoetching method, as a preparatory step prior to the formation of a resistor layer of a high sheet resistance--FIG. 1(b).
Step C: Impurity atoms, e.g. boron of a low concentration are introduced into the substrate through the window 5 by an ion implantation or a diffusion method, thus forming a resistor layer 6 of a high sheet resistance--FIG. 1(c).
Step D: The surface of the resistor layer 6 is oxidized to form an oxide film layer 7--FIG. 1(d).
Step E: After forming openings at the oxide film layer 7, contact electrodes 8 are formed to obtain electrical contact with the diffused impurity layers 4--FIG. 1(e).
The abovementioned conventional method of FIG. 1 has a drawback that controllability of the obtainable sheet resistance of the resistor layer 6 is imperfect since some parts of the impurity atoms for the resistor layer 6 are taken into the oxide film layer 7 when the surface of the resistor layer 6 is oxidized in the step D.
Another conventional method of making a resistor layer having a high sheet resistance in an IC device by use of an ion implantation is elucidated below by referring to FIG. 2(a)-FIG. 2(e). These figures are cross-sectional views illustrating the belowmentioned steps A to E of the second conventional making method:
Step A: As a first step, a semiconductor substrate 1 of e.g. n-type single crystalline silicon is oxidized to form an oxide film layer 2. A window 3 is then opened by a known photoetching method. A p-type impurity layer 4' is formed by an ion implantation of e.g. boron ions--FIG. 2(a).
Step B: The p-type impurity layer 4' is turned to a p-type thick layer 4" after a heat treatment at a high temperature. During the heat treatment, the surface of the p-type impurity layer 4' is also oxidized--FIG. 2(b).
Step C: An opening 5' is formed by a photoetching method. An n.sup.+ -type layer 6' lying shallower inside the p-type thick layer 4" is formed by an ion implantation through the opening 5'--FIG. 2(c).
Step D: The n.sup.+ -type layer 6' is turned to an n.sup.+ -type thick layer 6" after a high temperature treatment, during which treatment the surface of the n.sup.+ -type layer 6' is also oxidized. A p-type layer 7' lying between the n.sup.+ -type thick layer 6" and the n-type substrate 1 serves as a resistor region of a high sheet resistance. Both side ends of the p-type layer 7' are used as contact regions 71--FIG. 2(d).
Step E: Contact windows are formed on the contact regions 71 and then contact electrode bumps 8 are formed--FIG. 2(e).
The abovementioned second conventional method of FIG. 2 has the following problems.
The resistances of several resistor regions 7', each prepared by the second conventional method, differ from each other, since the ion implantation is made twice by using two kinds of impurity ions of opposite conductivity types. In addition, since the p-type layer 7' of a high sheet resistance is formed as a result of the depth difference between the n.sup.+ -type thick layer 6" and the p-type thick layer 4", the depths of both layers 6" and 4" must be strictly controlled. As shown in FIG. 3 (which is a graph showing impurity distribution profiles on a log scale after the ion implantation steps), the bottom front of the n.sup.+ -type thick layer 6" and that of the p-type thick layer 4" are set to be x.sub.1 and x.sub.2, respectively. The impurity distribution profiles of the n.sup.+ -type thick layer 6" and the p-type thick layer 4" are shown by curves 6 and 4, respectively. The impurity distribution profile shown by the curve 6 takes into account the compensation effect by the p-type impurity atoms in the p-type thick layer 4". The impurity distribution profile without such a compensation effect would be shown by a dotted curve 6'. The two curves 6 and 4 intersect with each other, thus the resultant compensated distribution profile for the p-type layer 7' shown by a curve 7 has a peak point "a". Accordingly, the resistance of the p-type layer 7' is determined by the depths x.sub.1 and x.sub.2 and the position of the point "a". This means that there are three parameters for the resistance determination of the p-type layer 7'. Therefore, the resistance control is bad.